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本专栏的目的是分享可以通过HDLBits仿真的Verilog代码 以提供参考 各位可同时参考我的代码和官方题解代码 或许会有所收益
题目链接：Rule90 - HDLBits
module top_module(input clk,input load,input [511:0] data,output [511:0] q );always @ (posedge clk) begin if (load) q <= data ; elseq <= {1'b0, q[511:1]} ^ {q[510:0], 1'b0} ;end
endmodule
题目链接：Rule110 - HDLBits
module top_module(input clk,input load,input [511:0] data,output [511:0] q
);always @(posedge clk) beginif (load) beginq <= data;endelse beginq <= (((q[511:0] ^ {q[510:0], 1'b0}) & q[511:1]) | ((q[511:0] | {q[510:0], 1'b0}) & (~q[511:1])));endend
endmodule题目链接：Conwaylife - HDLBits
module top_module(input clk,input load,input [255:0] data,output [255:0] q ); reg [255:0] q_next;reg [3:0] sum;always@(posedge clk) beginif(load)q <= data;else beginfor(int i=0; i<256; i++) begin //使用阻塞赋值，使sum得出后在该时钟周期内q立即变化，而不需要等到下个周期。if(i == 0) //左上角sum = q[1] + q[16] + q[17] + q[240] + q[241] + q[15] + q[31] + q[255];else if(i == 15) //右上角sum = q[14] + q[16] + q[0] + q[240] + q[254] + q[30] + q[31] + q[255];else if(i == 240) //左下角sum = q[0] + q[15] + q[239] + q[241] + q[1] + q[224] + q[225] + q[255];else if(i == 255) //右下角sum = q[0] + q[15] + q[14] + q[224] + q[238] + q[240] + q[239] + q[254];else if(0<i & i<15) //上边界sum = q[i-1] + q[i+1] + q[i+15] + q[i+16] + q[i+17] + q[i+239] + q[i+240] + q[i+241];else if(i%16 == 0) //左边界sum = q[i-1] + q[i+1] + q[i+15] + q[i+16] + q[i+17] + q[i-16] + q[i-15] + q[i+31];else if(i%16 == 15) //右边界sum = q[i-1] + q[i+1] + q[i+15] + q[i+16] + q[i-17] + q[i-16] + q[i-15] + q[i-31];else if(240<i & i<255) //下边界sum = q[i-1] + q[i+1] + q[i-17] + q[i-16] + q[i-15] + q[i-239] + q[i-240] + q[i-241];else //非边界sum = q[i-1] + q[i+1] + q[i-17] + q[i-16] + q[i-15] + q[i+15] + q[i+16] + q[i+17];case(sum) //根据邻居数量判断次态2:q_next[i] = q[i];3:q_next[i] = 1;default:q_next[i] = 0;endcaseendq = q_next;endend
endmodule